Home » Ask & Discuss » Board Exams - CBSE, ICSE, State Boards » Computer Science « Back to Discussion

Computer Science

New kid on the Block

Joined:	10 Mar 2010
Post:	1

10 Mar 2010 15:07:34 IST

0 People liked this

219

defined the logic gate

None

defined the logic gate

Share this article on:

Comments (3)

Transmigrator

Blazing goIITian

Joined: 21 May 2008

Posts: 426

10 Mar 2010 15:10:21 IST

Like 0 people liked this

A logic gate is a curcuit that establishes a logical relationship between the input and the output signals which can take only discreet values. The values are 0 and 1 that correspond to voltage inputs = 0 V and 5 V respectively..............

Neha Somani

Scorching goIITian

Joined: 19 Dec 2008

Posts: 288

19 Mar 2010 17:48:06 IST

Like 0 people liked this

above ans is right bt u hv to read urself hw logic circuit works i.e AND, OR, NOT & NAND gate these r basic gates...search on wikipedia or read some books on digital electronics..

edison

Forum Expert

Joined: 19 Oct 2006

Posts: 7449

31 Jan 2011 17:28:22 IST

Like 0 people liked this

There are digital circuits which either allow a signal to pass through or stop it. The circuits other wise called as gate allows the signal to pass only when some logical condition are satisfied. Under such condition the circuits are called logic gates. They are building blocks of any digital system. The basic logic gates are:

1. OR gate

2. AND gate and

3. NOT gate

Truth table is a table that shows all possible input combination and the corresponding output combination for a logic gate.

The Boolean algebra '+' or addition symbol is referred to as OR operation.

i.e. A + B (Read A or B)

The symbol '.' or multiplication symbol is referred to as AND operation.

i.e. A.B (Read A AND B)

The symbol (-) above the input i.e.

denotes negation or invesion..

Realisation of an OR gate using diodes

1. When both A and B are earthed (i.e. connected to low input 0), both the diodes do not conduct and no voltage develops across R. Therefore the voltage at C is zero with respect to earth. Hence the output Y is 0 (in levels).

2. When A = 0 and B = 1 (i.e., connected to positive terminal), the diode D₂ conducts but D₁ does not. Since D₂ is ideal, no voltage drop takes place across D₂ and a full voltage drop of 5V takes place across R at C, +5V with respect to earth. Therefore Y is 1 (in level).

3. When A = 1 and B = 0, D₁ conducts but D₂ does not. For the same reason as stated above the output Y is 1 (in level).

4. When A = 1 and B = 1, both diodes conducts since the diodes are ideal and connected in parallel, the voltage drop across R cannot exceed 5V, with C at +5V with respect to earth. Hence the output Y will be 1 (in level).

The truth table of OR gate

A	B	C
0	0	0
0	1	1
1	0	1
1	1	1

The AND gate

1. When A = 0 and B = 0 both diode D₁ and D₂ get forward biased and hence conduct. The diodes being ideal, no voltage drop takes place across either diode. Therefore potential difference of 5V takes place across R, with C at zero potential with respect to earth. Thus the output Y is 0 (in level).

2. When A = 0, B = 1, D₁ conducts diode D₂ will not. Since D₁ is ideal, no voltage drop occurs it. Therefore a voltage drop of 5V takes place across R, having D at +5V and C at zero with respect to earth. The output is 0 (in levels).

3. When A = 1, B = 0 for same reason, output is 0.

When A = 1, B = 1 none of diodes conduct and so no current flows through R. The potential at C is equal to potential at D which is +5V with respect to earth. Hence output Y is 1.

A	B	Y
0	0	0
0	1	0
1	0	0
1	1	1

The NOT gate

(i) When A = 0, the base of transistor also get earthed. Now emitter base function is not forward biased but base-collector function is reverse biased. As the emitter current is zero, the base current is also zero and hence the collector current will also be zero. Hence the output Y is 1 (in level).

(ii) When A = 1, the emitter base function gets forward biased. There will be emitter current, base current and collector current. The value of R_b and R_c can be adjusted so that large I_c can flow. The potential difference across R_c due to forward biasing of emitter is just 5V equal and opposite to the potential difference across R_c due to battery in collector circuit. Therefore the output is 0 (in level).

NOT gate is realised by transistor when A input is zero (grounded) so base is grounded.

All the voltage drops across collector and emitter, so we will get high output.

When A is given +5 voltage Base current increases consequentially collector current increases in common emitter configuration. Therefore voltage drop across Rc increase but voltage drop collects and emitter is zero, so output is zero.

Even giving high input at A out put is zero.

Combination of gates

NAND Gate

If the output of an AND gate is connected to the input of NOT gate then the logic gate is called NAND gate

NOR gate

If output of OR gate is connected to input of NOT gate, then the logic gate is called NOR gate

Truth table

Quick Reply

Reply

	Some HTML allowed.
	Keep your comments above the belt or risk having them deleted.
	Signup for a avatar to have your pictures show up by your comment
	If Members see a thread that violates the Posting Rules, bring it to the attention of the Moderator Team